Hi there 👋

Welcome to my blog. This is a place where I write random ideas that I think are useful for a CS major.

Although my writings are mostly about computer science, don’t be afraid to check them out!
You can find all sorts of things, ranging from how to make a digital circuit to how to pick a good dinner!
Don’t forget to check out my GitHub for my personal projects.

Going from Zero to Hero with Yosys and Verilator

Introduction Yosys and Verilator are two powerful free and open source tools that will help us automate verification, testing, simulation, and synthesis in our circuit designs. In this post, we will be implementing a half adder. Half Adder Truth table for a half adders is as follows: A B Sum Carry 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 Observe that...